morning:
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present: Kawagoe, Takeshita, JCB, Remi, Daniel, Roman
* Takeshita
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ECAL Base Unit, developed with DESY & Korea
EBU: 2011 summer 1 module ready
then rehearsal of afternoon session
afternoon
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present from HPK solid state div:
Yamamoto (director)
Sawaki, Inuzuka (sales div)
Yamamura, Kosugi
* Sawaki: intro to HPK solid state
* JCB: intro to LLR
* DJ: intro to LC, SiW ECAL
* RC: Si sensors
then discussion (largely Yamamoto)
- 2$/cm2 seems very cheap. some mention of 5$ (in japanese only)
- dead area at edge ~ 2*thickness
- future laser cutting of wafer: cleaner cut than diamond saw,
maybe able to reduce edge width
- 5 years production ~ OK
- 8" wafer
20/30% higher cost than 6", ~2*area (save on polishing)
8" assembly lines more developed, easier to extend
size trends upward
- lower quality Si, probably OK for <500 micron
- thick wafer not so good
- 8", 400-500 micron -> not too fragile
- new 8" production line just started production.
takes 2 years to complete
- leakage current requirement not major cost factor
those which fail are typically much above the requirement
- testing not very costly
- cost drivers:
material 20/30%
processing
# matrices per wafer
- 80-90% yield
- >50% no problem, ~20% one small defect
(these numbers not so consistent!)
- for 2011
stay with 6" wafer
internal HPK tests with 8"
* if OK then can send to us to test
- for 2012
parallel 6", 8"
- for DBD, keep with 6" technology
- 8" wafer for later (2013) incl. cost estimates
something like testbench for new HPK production line
- PhD topics: compare 6/8" end 2011?
co-supervise: Kobe/Shinshu/HPK - EP (HPK seem to prefer a Japanese)
- laser cutting. "T" cut. much better quality & control.
- dC/dV @ nominal bias voltage
- next step:
RC define looser requirements
production next summer
- HPK decide best design: depends on thickness
we are relatively flexible, but >300 micron (to limit fragility)
- HPK will try 2 or 3 different GR designs, cutting methods in 6"/8"
- visit again next spring (March) around CALICE mtg